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Cadence SPB OrCAD 16.60.032 H0tfix
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Cadence SPB OrCAD 16.60.032 Hotfix

Cadence SPB OrCAD 16.60.032 H0tfix

Cadence SPB OrCAD 16.60.032 Hotfix | 1.0 Gb

Cadence Design Systems Ltd., a world-renowned provider of EDA software, has released an hotfix 032 for Cadence SPB OrCAD 16.60, software a comprehensive package design of electronic circuits, analog and digital simulation, IC design of programmable logic and custom circuits, as well as the development and preparation for the production of printed circuit boards.

Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.

This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industry's first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.

DATE: 07-25-2014 HOTFIX VERSION: 032
381127 SPECCTRA CROSSTALK Specctra xtalk reports aren't correct
616770 ALLEGRO_EDITOR COLOR Remove the APPLY button in the Color Dialog window.
982944 ALLEGRO_EDITOR COLOR seperate the Etch to the Shape and the the Cline in the visibility window
982995 ALLEGRO_EDITOR INTERACTIV Shown infomation for the selected physical symbols
1024832 PSPICE PROBE Shows wrong data & header when exporting trace to .txt
1063258 PSPICE AA_OPT curve fit fails with error same data works in 16.5 Simulation error: out of range of data
1112360 PSPICE AA_OPT Advacne analysis gives runtime error while using Optimizer in attached design
1154323 PCB_LIBRARIAN VERIFICATION Con2con is choosing incorrect Primitive from Chips file and failing FTB Checks
1184690 CONCEPT_HDL CORE Weird behavior of genview for split hierarchical blocks
1212577 PSPICE MODELEDITOR IBIS translation fails without any information in log file
1213204 ALLEGRO_EDITOR PLACEMENT Place Manually with existing fixed net behaving incorrectly
1213837 ALLEGRO_EDITOR INTERACTIV When copying a stacked via the temp highlight does not display on the last layer of the stack.
1216519 SPECCTRA ROUTE Autorouter will not add BB via between uvia within the BGA area
1220655 PSPICE DEHDL_NETLISTER Support for automatic addition for Power source and Ground Node for Globals in DEHDL PSpice netlisting
1223018 CAPTURE OTHER Diff pair Auto Setup not working for the buses.
1225689 PSPICE AA_SMOKE Smoke analysis crashes with attached testcase
1232124 CONCEPT_HDL COMP_BROWSER unable to generate ppt_options.dat file in first go
1235059 PCB_LIBRARIAN IMPORT_CSV pin_delays not being imported into PDV
1238815 CAPTURE OTHER Capture doesn?t retain more than 191 library in add part/capture.ini under part selector configured libraries
1239241 ALLEGRO_EDITOR INTERACTIV Via replacement doesn't replace with correct via but right padstack name.
1240201 ALLEGRO_EDITOR EDIT_ETCH RPD DRC unresolved evenif HUD turns Green
1240314 PSPICE SIMULATOR Getting internal error,overflow for the second run
1242805 ALLEGRO_EDITOR DRC_CONSTR no_drc_progress_meter variable hangs allegro after running update drc
1243267 ADW TDA URL to TDO-SharePoint should be defined in CPM File
1244857 ADW TDA Policy File Variables not working correctly in policy file
1245779 CONCEPT_HDL CONSTRAINT_MGR Obsolete objects in DEHDL CM
1246811 CIS EXPLORER Option to keep the part type tree in CIS explorer expanded on every invoke
1246964 PSPICE PROBE Simulation Crashes in 16.6 but running successfully in 16.5
1248782 CONCEPT_HDL CORE Display winning physical bus names (occurrence mode) in the the lower block of an Hierarchical design
1249238 CONCEPT_HDL CORE Uprev from 16.3 splatters text around sch page
1249692 ALLEGRO_EDITOR GRAPHICS 3D Viewer is wrong when resizing its window.
1249850 ALLEGRO_EDITOR SHAPE With shape_rki_autoclip Route Keepin to Shape DRC is created
1250683 ALLEGRO_EDITOR INTERACTIV devpath corrupts if edited from user preferences.
1252059 ALLEGRO_EDITOR INTERACTIV Preference Editor is unable to delete a previous path entry for library paths
1253563 SIP_LAYOUT DEGASSING Not getting degassing voids when close to shape in center of design
1254319 ALLEGRO_EDITOR GRAPHICS ENH: Functionality to change the 3D Model color for more realistic view
1254562 ALLEGRO_EDITOR DATABASE Unable to delete a subclass that exist only on classes Package Keepout, Package Keepin and Route Keepin.
1255169 CONCEPT_HDL OTHER ADW (BPc) Packager should report the specific corrupt directive in the .cpm file
1255573 ALLEGRO_EDITOR DRC_CONSTR Need soldermask DRC checks when same net via and smd pad overlaps
1257950 CONSTRAINT_MGR SCHEM_FTB Changing xnet name on Allegro CM.
1258165 F2B DESIGNVARI changing visibility of Probe_number in variant schematic changes it to $Porbe_number
1258274 PCB_LIBRARIAN VERIFICATION con2con crash with no notification or error message
1258860 CAPTURE PROJECT_MANAGER Bug: Text Editor (File> New> VHDL File) filters characters from Text
1258872 CONCEPT_HDL CORE Objects are copied (instead of moved) when moved from sheet to sheet
1259284 CONCEPT_HDL PDF HDL_POWER ( global) net does not get transferred to the published pdf
1259375 CONCEPT_HDL CORE Help link to cdnUsers.org needs to be changed
1259860 ALLEGRO_EDITOR INTERACTIV Edit > Mirror does not display asymmetrical pad correctly when the footprint is attached to cursor.
1260002 ALLEGRO_EDITOR INTERACTIV Alt sym hard is not obeyed when using Edit > Move > Mirror
1260006 ALLEGRO_EDITOR PLACEMENT funckey r iange 90 rotation issue
1260667 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes when running AICC command on few Diff Pair traces.
1260763 CONCEPT_HDL CORE Export Physical fails with $TEMP entry in Setup-Tools
1260847 SIP_LAYOUT SYMB_EDIT_APPMOD Border texts seen as triangles.
1260948 ALLEGRO_EDITOR SHAPE Dynamic ground shape is shorting to via of a different net at layer 4 & 5 in this design
1262011 ALLEGRO_EDITOR PLACEMENT Key Properties on Component Instance/ Definition on available to use with Quickplace by Property
1262322 ALLEGRO_EDITOR PADS_IN Pads_in can not translate route keepout which specified for the all layers.
1262626 CONCEPT_HDL CORE PROBE NUMBER attributes lost from the nets after upreving the design
1263592 PCB_LIBRARIAN VERIFICATION Unable to check in Schematic Model due to pc.db file
1263685 ALLEGRO_EDITOR INTERACTIV Editing Photo Width value from non zero to zero allegro gives warning- Value must be greater or greater to zero
1263704 ALLEGRO_EDITOR EDIT_ETCH Bug - AiTR wrongly deletes blind vias and do reroutes.
1265120 ALLEGRO_EDITOR SHAPE Require voids in dynamic shapes to use pad value
1265275 ALLEGRO_EDITOR DRC_TIMING_CHK When XNETS are dissolved by removing the Models all Physical and Spacing NetClass associations are lost
1265633 PSPICE SIMULATOR Bias point result is different in consecutive simulation run of the attached project
1266349 ALLEGRO_EDITOR PLACEMENT Rotating symbol while placement show wrong angle of rotation than the placed angle when Angle is set in Design Parameter
1267541 PSPICE PROBE pspice.exe does not exit when run from command line
1267707 ALLEGRO_EDITOR PLACEMENT Mirror Command - preselect/postselect bug with general edit mode
1268299 PSPICE STABILITY Pspice crash on attached design
1270879 ALLEGRO_EDITOR COLOR Color view save creates .color file using older extension
1271295 SIP_LAYOUT DIE_STACK_EDITOR Die stack editor support needed for large variant combination designs.
1271385 CONCEPT_HDL CORE Locked property can still be added
1271853 APD OTHER When using the beta "shape to cline" command, add improved messages and partial completion of individual segs in error.
1272197 CONCEPT_HDL CORE concepthdl_menu.txt contains invalid Variants menu
1272318 CAPTURE GEN_BOM BOM_IGNORE not working for Capture BOM on hierarchical designs.
1272743 ALLEGRO_EDITOR PADS_IN PADS Library Translator does not open the Options dialog window.
1273517 F2B PACKAGERXL Netrev error - ERROR(40) Object not found in database
1274000 ALLEGRO_EDITOR DATABASE PCB layer can't be removed
1274530 ALLEGRO_EDITOR INTERACTIV Add Circle radius value changes next time using this command
1274697 PSPICE AA_MC pspiceaa crashes when running Advanced analysis monte carlo for the attached design
1275154 CONCEPT_HDL CORE Hierarchical Blocks lose ref designators when moved to another page
1275724 GRE CORE AiDT delete another clines
1275831 ALLEGRO_EDITOR DRC_CONSTR Waived DRCs return when using multi-thread DRC check
1275834 CONCEPT_HDL CORE ERROR (SPCOCD-569) on global bus
1276334 ALLEGRO_EDITOR PADS_IN PADS Library Import problem with outlines
1277062 ALLEGRO_EDITOR PLACEMENT Swapping parts from top to bottom Orientation changes
1278746 ALLEGRO_EDITOR DRC_CONSTR Package to package DRC allows place_bound_top in 0 spacing has drc in 16.6 version.
1278804 CONCEPT_HDL COPY_PROJECT Copy project crashes
1279362 ALLEGRO_EDITOR INTERACTIV User SKILL file makes Allegro Icons gone away
1279619 ALLEGRO_EDITOR DRC_CONSTR Netgroup in a Netclass doesn't inherit Spacing Cset
1279815 CONCEPT_HDL CORE Text > Change and RMB Editor does not allow multiple text edits
1279876 ALLEGRO_EDITOR DATABASE Using the Curved option in Fillets results in a pad to shape DRC
1280435 F2B BOM BOMHDL with variant repeats the PART_NUMBER value
1281669 CONCEPT_HDL COMP_BROWSER Match Any radio button in Component Browser didn't work.
1282001 ALLEGRO_EDITOR DRC_CONSTR Updating the DRCs on this design cause the DRC count to change on every update
1282480 SIP_LAYOUT WIREBOND Info on the Wire Count property needs to be updated indicating that it is a User Defined Property
1283952 ALLEGRO_EDITOR DescriptionTING Published pdf does not show dotted or phantom lines
1283957 ALLEGRO_EDITOR INTERACTIV Replace padstack in "Single Via Replace Mode" is changing netname of the vias with the latest hotfix of Allegro 16.6
1285588 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase control has wrong analysis result when add rectangle test bead in Clines.
1286743 ALLEGRO_EDITOR SHAPE Getting copper islands in the design after running the Delete Plating Bar command
1287215 ALLEGRO_VIEWER OTHER Allegro viewer plus does not support constraint regions
1288808 APD LOGIC Derive Assignment stalls out or won?t finish and appears to run out of database room.
1289251 ALLEGRO_EDITOR SCHEM_FTB Pin escapes (clines and vias) not inheriting new net name from a pin with a new net name.
1289293 F2B DESIGNVARI Warning 04: Cannot merge the variant properties on variant instance C119 component with same canonical path not present
1289809 SCM VERILOG_IMPORT User not able to import a verilog netlist into SCM
1290696 CONCEPT_HDL CORE Copying a net name repeatedly causes it to go off grid
1291162 CONCEPT_HDL CREFER crefer crashes when selecting generate cross refernece for all nets selected
1291285 SIP_LAYOUT IMPORT_DATA Replacing a Die with the Die Text in Wizard causes some Clines to Shift, creating new DRCs.
1291658 ALLEGRO_EDITOR INTERACTIV Cannot add Frectangle to Group
1292180 ALLEGRO_EDITOR SKILL Allegro Crash while performing query contents of "Maximum_Cavity_Size" with the skill command 'axlDBGetPropDictEntry'
1292210 CONCEPT_HDL CORE DEHDL crash if design was opened with -nonetlistuprev option.
1292278 SIP_LAYOUT WIREBOND When creating Wirebonds by Importing a Wirebond File, (wbt) the wirebonds are not on the correct Die layer
1292282 SIP_LAYOUT INTERACTIVE Getting Multiple GUIs when the Wirebond Import is open and we select outside the command GUI.
1293381 SIP_LAYOUT IMPORT_DATA Import SPD2 error
1293889 CONCEPT_HDL PAGE_MGMT page name regression result deleted by netassembler
1294124 ALLEGRO_EDITOR INTERACTIV Samsung Mobile division wants to disappear the grids in the display window when zoom-out function executes in the allegr
1294749 ALLEGRO_EDITOR ARTWORK Null pad is flagged as an error that break Thales automatic tape out
1294777 ALLEGRO_EDITOR SYMBOL Mechanical symbols missed on STEP result

About Cadence Design Systems, Inc.

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.

Name: Cadence SPB OrCAD
Version: (32bit) 16.60.032 Hotfix
Home: www.cadence.com
Interface: english
OS: Windows XP / Vista / Seven
System Requirements: Cadence SPB OrCAD 16.60.000 - 16.60.031
Size: 1.0 Gb





Категория: » Программы
Теги: Cadence, OrCAD, tfix

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